The present invention relates generally to dynamic random access memory (DRAM) design, and more particularly to signal timing control in embedded DRAM (eDRAM).
Integrated circuit design of a microelectronic chip is generally aimed at reducing the size of components and connections/spacings between components, as well as increasing processing speed while maintaining the integrity of data signals. Typically, a high performance microprocessor chip uses a high-speed cache memory, for storing, for example, instructions and data needed by a processor within the chip. The high-speed cache memory, referred to as the first level (L1) cache, is located proximate to the processor for maximizing efficiency and accuracy. The L1 cache memory is primarily made from static random access memory (SRAM) technology, such as a 6-transistor SRAM, which provides reliable performance. However, the SRAM takes up a very large area of the microprocessor chip.
Due to the size restriction of the L1 cache, upon the occurrence of a data miss, the processor issues commands to get data from an off-chip main memory. A high data miss rate results in a significant performance penalty. To overcome the problem associated with data misses, a second level of cache memory (L2) is provided on the microprocessor chip for storing, for example, instructions and data needed by the processor.
Embedded DRAMs (eDRAMs) with wide data bandwidth and wide internal bus width have been proposed for the L2 cache to replace conventional SRAM cache. Since each DRAM memory cell is formed by one transistor and a capacitor, the physical size of DRAM cache is significantly smaller than that of six-transistor SRAM for the same density. But serving as a L2 cache memory, the eDRAM has to operate at a greater speed, with a cycle time at 6 ns or less. This demands not only shorter cell access time but also tighter internal timing control of the eDRAM. FIG. 1 is a waveform showing timing relationships of some critical signals in a clock cycle Tc. Curve 110 is a word-line (WL) signal, which turns on a WL at time T1. Once the WL is turned on, a bit-line (BL) pair 120 starts to split. At time T2, when the BL pair 120 develops enough voltage differentiation, a sense-amplifier enable signal is activated to start sensing the BL voltage differentiation. After cell data being sensed, a column select signal is enabled at time T3 to allow data output. Then the WL is turned off at time T4. In order to prepare for a next cycle read, the BL starts to pre-charge at time T5 before the clock cycle Tc ends. In order for the eDRAM to function properly, the timings of T1, T2, T3, T4 and T5 are all tightly controlled. Especially, relationships of these timings must have sufficient margins at all specified process, voltage and temperature (PVT) conditions.
Traditional eDRAMs often use self timed delay chain to control the timings of the critical signals. But such delay chain may have different reactions to PVT variations than the core array, i.e., a timing relationship generated by the delay chain may not match what is required by the eDRAM cell array. In order to ensure that the eDRAM functions properly in all specified PVT conditions, circuit designers must design in greater timing margins, therefore the eDRAM operation speed will be slow down.
Using array device, e.g., building mini-arrays outside of the real array area, for timing tracking may solve the above mismatching problems, as the mini-arrays and the real arrays have the same structure, and may respond identically to PVT variations. But in most cases, adding mini-arrays in an already large chip is not practical.
As such, what is desired is timing control circuit that can precisely control delay time and automatically adapt to the clock signal variations for various internal control signals in an eDRAM.